View MX566AKCWG_7666553.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

max5713/max5714/max5715?4???8/10/12 ? ?/??(dac)??( ? ?2.048v2.500v4.096v)max5713/max5714/ max5715?2.7v5.5v??? (3mw)??????? ???100k (?)? max5713/max5714/max571550mhz?3spi/qspi ? /? microwire ? /dsp?????? ?? rdy dac??? 250 a???? 0.5mv?(?)?? ??max5713/max5714/max5715dac ??????? ???????????? ??????max5713/max5714/ max5715load?dac? (ldac)? ?( clr )?code?dac? dac?max5713/max5714/max5715 14 tssop ? ?12 wlp ? - 40 c + 125 c?? ? ???? ? ?? ???? ?? ?? ?? ? s ?dac? ? ?12? ? 1?lsb?inl? ? ? ? ??dac s ?????? ? 2.048v2.500v4.096v s ?? ? ??? ? 4.5s?? ? ?2k? s 5mm??4.4mm?14tssop??1.6mm?? ? 2.2mm?12wlp? s 2.7v5.5v?? s 1.8v5.5v ? v ddio ? s 50mhz?3spi/qspi/microwire/dsp? ?rdy s ??dac s ldac clr ? s ??? ? 1k?100k ? ?? 19-6394; rev 2; 1/13 ??????????????? ?????maxim?10800 ? 852 ? 1249 ? ()10800 ? 152 ? 1249 ? () maxim?china.maximintegrated.com ?? ??????? china.maximintegrated. com/max5713.related qspimotorola, ? inc.?? microwirenational ? semiconductor ? corporation.??? maxmaxim ? integrated ? products, ? inc.??? din sclk csb outa buffer por v dd gnd dac control logic power-down ref outb outc outd v ddio (rdy) clr (ldac) spi serial interface ( ) tssop package only 1ki 100ki code load clear / reset clear / reset code register dac latch 8- /1 0- /12-bit dac 1 of 4 dac channels internal reference/ external buffer max5713 max5714 max5715 max5713/max5714/max5715 ??8/10/12 dac??spi?
2 v dd , v ddio to gnd ................................................ -0.3v to +6v out_, ref to gnd ................................. ....-0.3v to the lower of (v dd + 0.3v) and +6v csb, sclk, ldac, clr to gnd ............................ -0.3v to +6v din, rdy to gnd ........................................ -0.3v to the lower of (v ddio + 0.3v) and +6v continuous power dissipation (t a = +70nc) tssop (derate at 10mw/ nc above 70nc) ................... 797mw wlp (derate at 16.1mw/ nc above 70nc) .................. 1288mw maximum continuous current into any pin .................... q50ma operating temperature range ........................ -40nc to +125nc storage temperature range ............................ -65nc to +150nc lead temperature (tssop only)(soldering, 10s) ........... +300nc soldering temperature (reflow) .................................... +260nc tssop junction-to-ambient thermal resistance ( ja ) ....... 100nc/w junction-to-case thermal resistance ( jc ) ............... 30nc/w wlp junction-to-ambient thermal resistance ( ja ) (note 2) ........................................................................ 62nc/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to china.maximintegrated.com/thermal-tutorial. note 2: visit china.maximintegrated.com/app-notes/index.mvp/id/1891 for information about the thermal performance of wlp packaging. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) electrical characteristics (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2ki, t a = -40nc to +125nc, unless otherwise noted. typical values are at t a = +25nc.) (note 3) parameter symbol conditions min typ max units dc performance (note 4) resolution and monotonicity n max5713 8 bits max5714 10 max5715 12 integral nonlinearity (note 5) inl max5713 -0.25 q0.05 +0.25 lsb max5714 -0.5 q0.25 +0.5 max5715 -1 q0. 5 +1 differential nonlinearity (note 5) dnl max5713 -0.25 q0.05 +0.25 lsb max5714 -0.5 q0.1 +0.5 max5715 -1 q0.2 +1 offset error (note 6) oe -5 q0.5 +5 mv offset error drift q10 fv/nc gain error (note 6) ge -1.0 q0.1 +1.0 %fs gain temperature coefficient with respect to v ref q3.0 ppm of fs/nc zero-scale error 0 10 mv full-scale error with respect to v ref -0.5 +0.5 %fs maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
3 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2ki, t a = -40nc to +125nc, unless otherwise noted. typical values are at t a = +25nc.) (note 3) parameter symbol conditions min typ max units dac output characteristics output voltage range (note 7) no load 0 v dd v 2ki load to gnd 0 v dd - 0.2 2ki load to v dd 0.2 v dd load regulation v out = v fs /2 v dd = 3v q10%, |i out | p 5ma 300 fv/ma v dd = 5v q10%, |i out | p 10ma 300 dc output impedance v out = v fs /2 v dd = 3v q10%, |i out | p 5ma 0.3 i v dd = 5v q10%, |i out | p 10ma 0.3 maximum capacitive load handling c l 500 pf resistive load handling r l 2 ki short-circuit output current v dd = 5.5v sourcing (output shorted to gnd) 30 ma sinking (output shorted to v dd ) 50 dc power-supply rejection v dd = 3v q10% or 5v q10% 100 fv/v dynamic performance voltage-output slew rate sr positive and negative 1.0 v/ fs voltage-output settling time ? scale to ? scale, to p 1 lsb, max5713 2.2 fs ? scale to ? scale, to p 1 lsb, max5714 2.6 ? scale to ? scale, to p 1 lsb, max5715 4.5 dac glitch impulse major code transition 7 nv*s channel-to-channel feedthrough (note 8) external reference 3.5 nv*s internal reference 3.3 digital feedthrough code = 0, all digital inputs from 0v to v ddio 0.2 nv*s power-up time startup calibration time (note 9) 200 fs from power-down 50 fs maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
4 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2ki, t a = -40nc to +125nc, unless otherwise noted. typical values are at t a = +25nc.) (note 3) parameter symbol conditions min typ max units output voltage-noise density (dac output at midscale) external reference f = 1khz 90 nv/hz f = 10khz 82 2.048v internal reference f = 1khz 112 f = 10khz 102 2.5v internal reference f = 1khz 125 f = 10khz 110 4.096v internal reference f = 1khz 160 f = 10khz 145 integrated output noise (dac output at midscale) external reference f = 0.1hz to 10hz 12 fv p-p f = 0.1hz to 10khz 76 f = 0.1hz to 300khz 385 2.048v internal reference f = 0.1hz to 10hz 14 f = 0.1hz to 10khz 91 f = 0.1hz to 300khz 450 2.5v internal reference f = 0.1hz to 10hz 15 f = 0.1hz to 10khz 99 f = 0.1hz to 300khz 470 4.096v internal reference f = 0.1hz to 10hz 16 f = 0.1hz to 10khz 124 f = 0.1hz to 300khz 490 output voltage-noise density (dac output at full scale) external reference f = 1khz 114 nv/hz f = 10khz 99 2.048v internal reference f = 1khz 175 f = 10khz 153 2.5v internal reference f = 1khz 200 f = 10khz 174 4.096v internal reference f = 1khz 295 f = 10khz 255 integrated output noise (dac output at full scale) external reference f = 0.1hz to 10hz 13 fv p-p f = 0.1hz to 10khz 94 f = 0.1hz to 300khz 540 2.048v internal reference f = 0.1hz to 10hz 19 f = 0.1hz to 10khz 143 f = 0.1hz to 300khz 685 2.5v internal reference f = 0.1hz to 10hz 21 f = 0.1hz to 10khz 159 f = 0.1hz to 300khz 705 4.096v internal reference f = 0.1hz to 10hz 26 f = 0.1hz to 10khz 213 f = 0.1hz to 300khz 750 maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
5 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2ki, t a = -40nc to +125nc, unless otherwise noted. typical values are at t a = +25nc.) (note 3) parameter symbol conditions min typ max units reference input reference input range v ref 1.24 v dd v reference input current i ref v ref = v dd = 5.5v 55 74 fa reference input impedance r ref 75 100 ki reference ouput reference output voltage v ref v ref = 2.048v, t a = +25nc 2.043 2.048 2.053 v v ref = 2.5v, t a = +25nc 2.494 2.500 2.506 v ref = 4.096v, t a = +25nc 4.086 4.096 4.106 reference temperature coefficient (note 10) max5715a q3.7 q10 ppm/nc max5713/max5714/max5715b q10 q25 reference drive capacity external load 25 ki reference capacitive load 200 pf reference load regulation i source = 0 to 500fa 2 mv/ma reference line regulation 0.05 mv/v power requirements supply voltage v dd v ref = 4.096v 4.5 5.5 v all other options 2.7 5.5 i/o supply voltage v ddio 1.8 5.5 v supply current (note 11) i dd internal reference v ref = 2.048v 0.93 1.25 ma v ref = 2.5v 0.98 1.30 v ref = 4.096v 1.16 1.50 external reference v ref = 3v 0.85 1.15 v ref = 5v 1.10 1.40 interface supply current (note 11) i ddio 1 fa power-down mode supply current i pd all dacs off, internal reference on 140 fa all dacs off, internal reference off, t a = -40nc to +85nc 0.5 1 all dacs off, internal reference off, t a = +125nc 1.2 2.5 digital input chracteristics (csb, sclk, din, ldac, clr) hysteresis voltage v h 0.15 v input high voltage v il 2.2v < v ddio < 5.5v 0.7x v ddio v 1.8v < v ddio < 2.2v 0.8x v ddio maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
6 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2ki, t a = -40nc to +125nc, unless otherwise noted. typical values are at t a = +25nc.) (note 3) parameter symbol conditions min typ max units input low voltage (note 11) v il 2.2v < v ddio < 5.5v 0.3 x v ddio v 1.8v < v ddio < 2.2v 0.2 x v ddio input leakage current i in v in = 0v or v ddio (note 11) q0.1 q1 fa input capacitance (note 10) c in 10 pf digital output (rdy) output high voltage v oh v ddio > 2.5v, i source = 3ma v ddio - 0.2 v v ddio > 1.8v, i source = 2ma v ddio - 0.2 v output low voltage v ol v ddio > 2.5v, i sink = 3ma 0.2 v v ddio > 1.8v, i sink = 2ma 0.2 v output short-circuit current i oss i sink , i source 100 ma spi timing characteristics (csb, sclk, din, rdy) sclk frequency f sclk 2.7v < v ddio < 5.5v, standalone, daisy chain (note 12) 0 50 mhz 0 20 1.8v < v ddio < 2.7v, standalone, daisy chain (note 12) 0 33 0 20 sclk period t sclk 2.7v < v ddio < 5.5v 20 ns 1.8v < v ddio < 2.7v 30 sclk pulse width high t ch 8 ns sclk pulse width low t cl 8 ns csb fall to sclk fall setup time t css0 to first sclk falling edge 8 ns csb fall to sclk fall hold time t csh0 applies to inactive sclk falling edge preceding the first sclk falling edge 0 ns csb rise to sclk fall hold time t csh1 applies to the 24th sclk falling edge 0 ns csb rise to sclk fall t csa applies to the 24th sclk falling edge, aborted sequence 12 ns sclk fall to csb fall t csf applies to 24th sclk falling edge 100 ns csb pulse width high t cspw 20 ns din to sclk fall setup time t ds 5 ns din to sclk fall hold time t dh 4.5 ns clr pulse width low t clpw 20 ns clr rise to csb fall t csc required for command to be executed 20 ns ldac pulse width low t ldpw 20 ns ldac fall to sclk fall hold t ldh a pplies to 24th sclk falling edge, 20 ns maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
7 ?1. ? spi??? 7 maxim integrated max5713/max5714/max5715 ultra-small, quad-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface note 3: electrical specifications are production tested at t a = +25c. specifications over the entire operating temperature range are guaranteed by design and characterization. typical specifications are at t a = +25c and are not guaranteed. note 4: dc performance is tested without load. note 5: linearity is tested with unloaded outputs to within 20mv of gnd and v dd . note 6: offset and gain errors are calculated from measurements made with v ref = v dd at code 30 and 4065 for max5715, code 8 and 1016 for max5714, and code 2 and 254 for max5713. note 7: subject to zero and full-scale error limits and v ref settings. note 8: measured with all other dac outputs at midscale with one channel transitioning 0 to full scale. note 9: on power-up, the device initiates an internal 200s (typ) calibration sequence. all commands issued during this time will be ignored. note 10: guaranteed by design. note 11: all channels active at v fs , unloaded. static logic inputs with v il = v gnd and v ih = v ddio . note 12: daisy-chain speed is relaxed to accommodate (t crf + t css0 ) with margin (derived specification, not production tested). note 13: this specification and its propagation through the chain limits how quickly an aborted daisy-chain command can be fol- lowed by another daisy-chain command, to be applied on a per-device basis. figure 1. spi serial interface timing diagram electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 3) parameter symbol conditions min typ max units sclk fall to rdy fall t crf a pplies to 24th sclk falling edge, c load = 20pf 40 ns sclk fall to rdy hold t crh a pplies to 24th sclk falling edge, c load = 0pf 2 ns csb rise to rdy rise t csr c load = 20pf (note 13) 40 ns d in 23 d in 22 d in 21 d in 20 d in 19 d in 18 d in 17 d in 16 d in 2 d in 1 t csa t csf t ldpw t ldh t csh1 d in 0 d in 23 1 sclk csb din 23 45 67 82 22 32 41 t csh0 t cspw t clpw t csc t css0 t ch t cl t dh t ds t sclk ldac clr d in 23 d in 22 d in 21 d in 20 d in 19 d in 18 d in 17 d in 16 d in 2 d in 1 t csa t csf t ldpw t ldh t csh1 d in 0 d in 23 1 sclk csb din 23 45 67 82 22 32 41 t csh0 t cspw t clpw t csc t css0 t ch t cl t dh t ds t sclk ldac clr maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
8 ? (max5715, 12-bit performance, t a = +25c, unless otherwise noted.) ?2. ? ?spi???(???tssop?) d in 23x in clk csb rdy d in 22 d in 21 d in 20 d in 19 d in 18 d in 17 d in 16 d in 2 d in 1 d in 0 d in 23 123 45 67 82 22 32 4 t crh t csf t crf 25 t csr t ch t cl t sclk t ds t dh t csh0 t cspw t css0 inl vs. code max5713 toc01 code (lsb) inl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 3v no load inl vs. code max5713 toc02 code (lsb) inl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 5v no load dnl vs. code max5713 toc03 code (lsb) dnl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 3v no load maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
9 ?() (max5715, 12-bit performance, t a = +25c, unless otherwise noted.) dnl vs. code max5713 toc04 code (lsb) dnl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 5v no load inl and dnl vs. supply voltage max5713 toc05 supply voltage (v) error (lsb) 5.1 4.7 3.9 4.3 3.5 3.1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 max inl v ref = 2.7v 1.0 -1.0 2.7 5.5 max dnl min dnl min inl inl and dnl vs. temperature max5713 toc06 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 error (lsb) -0.8 -0.6 -0.4 -0.2 0.2 0 0.4 0.6 0.8 1.0 -1.0 max inl v dd = v ref = 3v max dnl min dnl min inl offset and zero-scale error vs. supply voltage max5713 toc07 supply voltage (v) error (mv) 5.1 4.7 3.9 4.3 3.5 3.1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 2.7 5.5 zero-scale error offset error v ref = 2.5v (external) no load offset and zero-scale error vs. temperature max5713 toc08 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 error (mv) -0.8 -0.6 -0.4 -0.2 0.2 0 0.4 0.6 0.8 1.0 -1.0 v ref = 2.5v (external) no load offset error (v dd = 5v) offset error (v dd = 3v) zero-scale error full-scale error and gain error vs. supply voltage max5713 toc09 supply voltage (v) error (%fs) 5.1 4.7 3.9 4.3 3.5 3.1 -0.016 -0.012 -0.008 -0.004 0 0.004 0.008 0.012 0.016 v ref = 2.5v (external) no load 0.020 -0.020 2.7 5.5 full-scale error gain error full-scale error and gain error vs. temperature max5713 toc10 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 error (%fsr) -0.05 0 0.05 0.10 -0.10 v ref = 2.5v (external) no load gain error (v dd = 3v) gain error (v dd = 5v) full-scale error supply current vs. temperature max5713 toc11 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 supply current (ma) 0.6 0.8 1.0 1.4 1.2 0.4 out_ = full scale no load v ref (external) = v dd = 3v v ref (external) = v dd = 5v v ref (internal) = 2.5v, v dd = 5v v ref (internal) = 2.048v, v dd = 5v v ref (internal) = 4.096v, v dd = 5v supply current vs. supply voltage max5713 toc12 v dd (v) 5.1 4.7 3.9 4.3 3.5 3.1 2.7 5.5 v ref (internal) = 4.096v supply current (ma) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 no load t a = +25c v ref (internal) = 2.5v v ref (external) = 2.5v v ref (internal) = 2.048v maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
?() (max5715, 12-bit performance, t a = +25c, unless otherwise noted.) 10 maxim integrated power-down mode supply current vs. temperature max5713 toc13 supply voltage (v) 5.1 3.5 3.9 4.3 4.7 3.12.7 5.5 power-down supply current (a) 0.4 0.8 1.6 1.2 0 power-down mode all dacs t a = -40c t a = +25c t a = +85c t a = +125c supply current vs. code max5713 toc14 code (lsb) 4000 3500 3000 2500 2000 1500 1000 500 0 4500 supply current (ma) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 no load t a = +25c v dd = 5v, v ref (external) = 5v v dd = 5v, v ref (internal) = 4.096v v dd = 5v, v ref (internal) = 2.048v v dd = 5v, v ref (internal) = 2.5v v dd = 5v, v ref (external) = 3v i ref (external) vs. code max5713 toc15 code (lsb) reference current ( a) 3584 3072 2560 2048 1536 1024 10 20 30 40 50 60 0 5120 4096 v dd = v ref no load v ref = 5v v ref = 3v max5713 toc17 trigger pulse 5v/div v out 0.5v/div zoomed v out 1 lsb/div 4s/div 4.3s settling to 1 lsb (v dd = v ref = 5v, r l = 2ki , c l = 200pf) 3/4 scale to 1/4 scale max5713 toc16 trigger pulse 5v/div v out 0.5v/div zoomed v out 1 lsb/div 4s/div settling to 1 lsb (v dd = v ref = 5v, r l = 2ki , c l = 200pf) 3.75s 1/4 scale to 3/4 scale max5713 toc18 trigger pulse 5v/div 1 lsb change (midcode transition 0x7ff to 0x800) glitch energy = 6.7nv?s zoomed v out 3.3mv/div 2s/div major code transition glitch energy (v dd = v ref = 5v, r l = 2ki , c l = 200pf) max5713/max5714/max5715 ??8/10/12 dac??spi?
?() (max5715, 12-bit performance, t a = +25c, unless otherwise noted.) 11 maxim integrated major code transition glitch energy (v dd = v ref = 5v, r l = 2ki , c l = 200pf) max5713 toc19 2s/div trigger pulse 5v/div zoomed v out 3.3mv/div 1 lsb change (midcode transition 0x800 to 0x7ff) glitch energy = 6nv?s v out vs. time transient exiting power-down max5713 toc20 dac output 500mv/div 10s /div v sclk 5v/div 0v 0v v dd = 5v, v ref = 2.5v external 24th edge power-on reset to 0v max5713 toc21 v out 2v/div 20s /div v dd 2v/div 0v 0v v dd = v ref = 5v 10ki load to v dd channel-to-channel feedthrough (v dd = v ref = 5v, t a = +25n c, no load) max5713 toc23 5s /div no load no load trigger pulse 10v/div static dac 1.25mv/div transitioning dac 1v/div transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 1.8nv*s channel-to-channel feedthrough (v dd = v ref = 5v, t a = +25n c, r l = 2ki , c l = 200pf) max5713 toc22 4s /div trigger pulse 10v/div transitioning dac 1v/div r l = 2k i no load static dac 1.25mv/div transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 3.5nv*s channel-to-channel feedthrough (v dd = 5v, v ref = 4.096v (internal), t a = +25n c, r l = 2ki , c l = 200pf) max5713 toc24 5s /div trigger pulse 10v/div no load static dac 1.25mv/div transitioning dac 1v/div transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 3.3nv*s r l = 2k i max5713/max5714/max5715 ??8/10/12 dac??spi?
12 ?() (max5715, 12-bit performance, t a = +25c, unless otherwise noted.) max5713 toc25 trigger pulse 10v/div transitioning dac 1v/div static dac 1.25mv/div no load no load 4s/div channel-to-channel feedthrough (v dd = 5v, v ref = 4.096v (internal), t a = +25n c, no load) transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 1.1nv*s max5713 toc26 400ns/div digital feedthrough v dd = v re f = 5v r l = 10k 0.7mv/div digital feedthrough -0.1nvs output load regulation max5713 toc27 i o ut (ma) d v out (mv) 50 40 20 30 -10 0 10 -20 -8 -6 -4 -2 0 2 4 6 8 10 -10 -30 60 v dd = v ref v dd = 5v v dd = 3v headroom at rails vs. output current (v dd = v ref ) max5713 toc29 i out (ma) v out (v) 9 8 6 7 2 3 4 5 1 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 0 01 0 v dd = 5v, sourcing v dd = 3v, sourcing v dd = 3v and 5v sinking dac = zero scale dac = full scale output current limiting max5713 toc28 i out (ma) d v out (mv) 60 50 30 40 -10 0 10 20 -20 -400 -300 -200 -100 0 100 200 300 400 500 -500 -30 70 v dd = v ref v dd = 5v v dd = 3v noise-voltage density vs. frequency (dac at midscale) max5713 toc30 frequency (hz) noise-voltage density (nv/ hz) 10k 1k 50 100 150 200 250 300 350 0 100 100k v dd = 5v, v ref = 2.048v (internal) v dd = 5v, v ref = 4.5v (external) v dd = 5v, v ref = 4.096v (internal) v dd = 5v, v ref = 2.5v (internal) maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
13 ?() (max5715, 12-bit performance, t a = +25c, unless otherwise noted.) 0.1hz to 10hz output noise, external reference (v dd = 5v, v ref = 4.5v) max5713 toc31 2v/div midscale unloaded v p-p = 12v 4s/div 0.1hz to 10hz output noise, internal reference (v dd = 5v, v ref = 2.048v) max5713 toc32 2v/div midscale unloaded v p-p = 13v 4s/div 0.1hz to 10hz output noise, internal reference (v dd = 5v, v ref = 2.5v) max5713 toc33 2v/div midscale unloaded v p-p = 15v 4s/div v ref drift vs. temperature max5713 toc35 temperature drift (ppm/c) percent of population (%) 5.0 4.5 4.0 3.5 3.0 2.5 10 20 30 40 50 60 0 2.0 5.5 v dd = 2.7v, v ref = 2.5v (internal), box method 0.1hz to 10hz output noise, internal reference (v dd = 5v, v ref = 4.096v) max5713 toc34 2v/div midscale unloaded v p-p = 16v 4s/div reference load regulation max5713 toc36 reference output current (a) dv ref (mv) 450 400 350 300 250 200 150 100 50 -0.8 -0.6 -0.4 -0.2 0 -1.0 0 500 v dd = 5v internal reference v ref = 2.048v, 2.5v, and 4.096v supply current vs. logic voltage max5713 toc37 input logic voltage (v) supply current (a) 4 3 2 1 300 600 900 1200 1500 1800 2100 2400 2700 3000 0 05 v ddio = 5v v ddio = 3v v ddio = 1.8v maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
14 /? / tssop wlp 1 b1 ref ??/ 2 a1 outa ?a ? dac 3 a2 outb ?b ? dac 4 b2 gnd ? 5 a3 outc ?c ? dac 6 a4 outd ?d ? dac 7 b4 v dd ???0.1 f?v dd gnd 8 rdy spi ? rdy??rdy?csb 9 c4 din spi?? 10 c3 sclk spi??? 11 c2 csb spi??? 12 c1 clr ??? 13 b3 v ddio ????? 14 ldac ?dac????dac? 14 13 12 11 10 9 8 1 2 3 4 5 6 7 ldac v ddio clr csb gnd outb outa ref top view max5713 max5714 max5715 sclk din rdy v dd outd outc tssop + wlp top view din clr v dd ref outd outa max5713/max5714/max5715 + 1 2 34 a csbs clk gnd v ddio outb outc b c maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
15 ?? max5713/max5714/max5715?4???8/10/12 ? ?dac2.7v5.5v??? ????????? ??100k ??? ?????2.048v2.5v 4.096v 50mhz?3spi/qspi/microwire/ dsp???????? y?????max5713/max5714/max5715 /??codedac??y (por)dac????? clr?????? dac(out_) max5713/max5714/max5715?dac ?dac??? ?1v/ s?(?)2k () 500pf?()????(v dd )? ? gndv dd ? gnd??2k ?gnd v dd 200mv??v dd ??2k ? v dd gnd200mv?? dac?? out ref n d vv 2 = ?d ? = ? ?dac???v ref ? = ? ?? n ? = ? ?? ??? ??dac???? ?????? ?dac?? ?dac?code??dac? ( ??? )code??r dac??dac?code? codecode_load??dac? ??dacdac???? ??code_loadload ldac???code???? ?????codedac?? dac???????? ?codeload??? sw_clearsw_reset??codedac? ????? ?? max5713/max5714/max5715????? ?2.048v2.500v4.096v??? ?ref????( ? ) 25k ?? ?? ????100k ?? + 1.24v v dd ?refgnd???? ??max5713/max5714/max5715?? ????????? china.maximintegrated.com/products/references/ ?dac ? ( ldac ) (tssop?) max5713/max5714/max5715 ? ldac ??dac????? ??? ldac v ddio ?? ldac ??? ldac ????code? ?dac ldac ???? ?dac???code?dac dacconfig ?dacldac maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
16 (clr ) max5713/max5714/max5715??? clr ? ??????dac?? clr ????codedac?? ??spi?spi? clr ???t csc ?? ???(v ddio ) max5713/max5714/max5715??(1.8v 5.5v)??(v ddio )v ddio i/o? spi? max5713/max5714/max5715?3??microwire ? spiqspidsp????sclkcsb ? din??(csb??)? (din)????csb????? ???(sclk)??? ???24dac ??1??24sclk??24 ??????? ?spicsb????? ???????? csb?????sclk??? ??24sclk?spi?24 sclk??????3??? 24sclk?spispi? ??????? ?1??3??????? ?max5713/max5714/max5715dac ( 1 )????? 2 ?3 ??spi??? spi?/ rdy ? (tssop?) ? ??????tssop max5713/max5714/max5715 rdy ? ?csb?max5713/max5714/max5715 ? ?24sclk?? rdy ?? ?25sclk???spi?2?? ?spi?????(t crf ? + t css0 ) ??spi???????? ???????t csa ?? ??4?????? 1. ? dac??? part b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 max5713 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x max5714 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x max5715 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
17 spi??? max5713/max5714/max5715?? ?? 2????? ?4. ? spi??? ?3. ? spi?? max5713 max5714 max5715 csb sclk din csb sclk din * csb sclk din *additional spi device csb1 sclk mosi c rdy rdy max5713 max5714 max5715 csb sclk din csb sclk din * * dout csb csb3 csb2 miso sclk din *additional spi device csb1 sclk mosi c maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
18 2. ? spi command b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 description dac commands coden 0 0 0 0 dac selection code register data [11:4] code register data [3:0] x x x x writes data to the selected code register(s) loadn 0 0 0 1 dac selection x x x x x x x x x x x x x x x x transfers data from the selected code register(s) to the selected dac register(s) coden_ load_all 0 0 1 0 dac selection code register data [11:4] code register data [3:0] x x x x simultaneously writes data to the selected code register(s) while updating all dac registers coden_ loadn 0 0 1 1 dac selection code register data [11:4] code register data [3:0] x x x x simultaneously writes data to the selected code register(s) while updating selected dac register(s) configuration commands power 0 1 0 0 0 0 power mode 00 = normal 01 = pd 1ki 10 = pd 100ki 11 = pd hi-z x x x x dac d dac c dac b dac a x x x x x x x x sets the power mode of the selected dacs (dacs selected with a 1 in the corresponding dacn bit are updated, dacs with a 0 in the corresponding dacn bit are not impacted) sw_clear 0 1 0 1 0 0 0 0 x x x x x x x x x x x x x x x x executes a software clear (all code and dac registers cleared to their default values) sw_reset 0 1 0 1 0 0 0 1 x x x x x x x x x x x x x x x x executes a software reset (all code, dac, and control registers returned to their default values) maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
19 2. ? spi() command b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 description config 0 1 1 0 all dacs 0 0 ld_en x x x x dac d dac c dac b dac a x x x x x x x x sets the dac latch mode of the selected dacs. only dacs with a 1 in the selection bit are updated by the command. ld_en = 0: dac latch is operational (load and ldac controlled) ld_en = 1: dac latch is transparent ref 0 1 1 1 0 ref power 0 = dac 1 = on ref mode 00 = ext 01 = 2.5v 10 = 2.0v 11 = 4.1v x x x x x x x x x x x x x x x x sets the reference operating mode. ref power (b18): 0 = internal reference is only powered if at least one dac is powered 1 = internal reference is always powered all dac commands code_all 1 0 0 0 0 0 0 0 code register data [11:4] code register data [3:0] x x x x writes data to all code registers load_all 1 0 0 0 0 0 0 1 x x x x x x x x x x x x x x x x updates all dac latches with current code register data code_ all_ load_all 1 0 0 0 0 0 1 x code register data [11:4] code register data [3:0] x x x x simultaneously writes data to all code registers while updating all dac registers no operation commands no operation 1 0 0 1 x x x x x x x x x x x x x x x x x x x x these commands will have no effect on the device 1 0 1 x x x x x x x x x x x x x x x x x x x x x 1 1 x x x x x x x x x x x x x x x x x x x x x x reserved commands: any commands not specifically listed above are reserved for maxim internal use only. maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
20 coden coden(b[23:20]?=?0000)?daccode? ??code???dac ldac ??????dac?? coden?dac?selection?? dac?code_all ? (b[23:16]?=? 10000000) 2?3 loadn loadn(b[23:20]?=?0001)??code??? ? ??dacdac?dac?selection ??dac?loadn??? dac?load_all?(b[23:16]?= ? 10000001) 2?3 coden_load_all coden_load_all (b[23:20]?=?0010) ?dac code????dacdac?? ??dac ldac code? ??????? ? ?dac_address??dac?code_all_ ? load_all?(b[23:16]?=?1000001x)?coden_ ? load_all??code??? ? dac ? selection ? ? dac loadn?load_all 2 3 coden_loadn coden_loadn (b[23:20]?=?0011) ?dac code????dacdac?? ??dac ldac code? ???????? dac ? selection ??dac?code_all_ load_all 2?3 code_all code_all(b[23:16]?=?10000000)?daccode ??2 load_all load_all (b[23:16]?=?10000001)? ? code ????dacdac?? 2 code_all_load_all code_all_load_all(b[23:16]?=?1000001x)? daccode????dacdac? ?2 3. ? dac? b19 b18 b17 b16 dac selected 0 0 0 0 dac a 0 0 0 1 dac b 0 0 1 0 dac c 0 0 1 1 dac d x 1 x x all dacs 1 x x x all dacs maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
21 power max5713/max5714/max5715 ? ? ? (power)(b[23:20]?=?0100)power? dac?????dac????? ?b[17:16]b[11:8]?? dac?dac??standby?? ???dac???? ?????? 5???? ????????dac?? ??????????? standby????????? ????standby???? ??ref?4 sw_resetsw_clear sw_reset?(b[23:16]?=?01010001)sw_clear ? (b[23:16]?=?01010000)??? ?sw_clear?? codedac???sw_reset ?codedac???? 4. ? power ? (100)? 5. ? ?dac????? b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 0 0 0 pd1 pd0 x x x x d c b a x x x x x x x x power command power mode: 00 = normal 01 = 1ki 10 = 100ki 11 = hi-z dont care multiple dac selection: 1 = dac selected 0 = dac not selected dont care default values (all dacs) ? 0 0 x x x x 1 1 1 1 x x x x x x x x pd1 ? (b17) pd0 ? (b16) ?? 0 0 0 1 ???1k?gnd 1 0 ???100k ?gnd 1 1 ?? maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
22 config config (b[23:20]?=?0110) ?dac ldac load???b16?=?0dac b16?=?1?dac? ??dac???dac??? ??dacb[11:8]?6 ref ref?dac???? b[17:16]?=?00dac???b[17:16] ?011011 ? 2.5v2.048v4.096v ?? refrf2?(b18)?0?(??)?dac ? ??????(standby??) rf2?(b18?=?1)?1??dac??? ?????? 1 a???7 6. ? config? 7. ? ref? b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 1 1 0 rf2 rf1 rf0 x x x x x x x x x x x x x x x x ref command 0 = off in standby 1 = on in standby ref mode: 00 = ext 01 = 2.5v 10 = 2.0v 11 = 4.0v dont care dont care default values ? 0 0 0 x x x x x x x x x x x x x x x x b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 1 0 all 0 0 ldb x x x x d c b a x x x x x x x x config command 0 = select individual dacs 1 = select all dacs config command 0 = normal 1 = transparent dont care multiple dac selection: 1 = dac selected 0 = dac not selected dont care default values (all dacs) ? 0 x x x x 1 1 1 1 x x x x x x x x maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
23 ?? ?y(por) ?v dd v ddio ?dac????dac ???????? (200 s?) ? ?????v dd v ddio ? ?????gnd ?? ? gnd???????dac ??gnd????dac??? ?????? ?????? ?max5713/max5714/max5715gnd ????????? ??? ???????max5713/ max5714/max5715??? ?(inl) inl???? ??? ??(dnl) dnl???1?lsb??dnl? ?1?lsbdac????dnl? ?1?lsbdac?? ? ?????????? ?????? ???? ?????? ??????? ?dac?0??? ??? ?dac?????? ??? ? ?????dac?(? ?)??? ? ??dac??dac? /?? ?????msb????? ???????msb ??????????? ?????? /??^ /??????????? ???? maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
24 ??? outa buffer a dac control logic power-down 1ki 100ki code load clear / reset clear / reset code register a dac latch a 8- /1 0- /1 2- bit dac a outb buffer b dac control logic power-down 1ki 100ki code load clear / reset clear / reset code register b dac latch b 8- /1 0- /1 2- bit dac b outc buffer c dac control logic power-down 1ki 100ki code load clear / reset clear / reset code register c dac latch c 8- /1 0- /1 2- bit dac c outd buffer d dac control logic power-down 1ki 100ki code load clear / reset clear / reset code register d dac latch d 8- /1 0- /1 2- bit dac d din sclk csb v ddio por (rdy) clr (ldac) spi serial interface ref 100ki r in internal/external reference (user option) max5713 max5714 max5715 () tssop package only v dd gnd maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
25 ? dac c csb sclk din out gnd ldac v ddio v dd ref 100nf 100nf 4.7f max5713 max5714 max5715 clr note: unipolar operating circuit, one channel shown v ddio v dd dac c csb sclk din out gnd ldac v ddio v dd ref 100nf 100nf 4.7f r1 r2 r1 = r2 max5713 max5714 max5715 clr note: bipolar operating circuit, one channel shown v ddio v dd maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
26 ? ??-40 c+125 c??? + ??(pb)/rohs??? t ? = ? ? * ??? ?? process: bicmos ?? ?????(?)? china. maximintegrated.com/packages ???? + # - ?rohs???????? ?????rohs???? -? ?() ????(ppm/c) max5713aud+t* 14 tssop 8 10 (typ) max5714aud+t* 14 tssop 10 10 (typ) max5715aaud+t 14 tssop 12 3 (typ),10 (max) max5715baud+t* 14 tssop 12 10 (typ) max5715awc+t 12 wlp 12 3 (typ),10 (max) ? ? ?? 14 tssop u14+1 21-0066 90-0113 12 wlp w121b2+1 21-0009 ????1891 maxim integrated max5713/max5714/max5715 ??8/10/12 dac??spi?
?? ? ? ? ?? 0 7/12 1 10/12 ??? 5, 9, 10, 12, 13, 25, 26 2 11/13 ?? 7, 26 maximmaxim????????maxim??????????? ???(??)?????? maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-10 00 27 ? 2013 maxim integrated maxim?maxim ? integratedm axim ? integrated ? products, ? inc. ? maxim 8328 ? 100083 ?800 ? 810 ? 0310 010-6211 ? 5199 010-6211 ? 5299 max5713/max5714/max5715 ??8/10/12 dac??spi?

▲Up To Search▲

Price & Availability of MX566AKCWG

	To Download MX566AKCWG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .